1. Field of Invention
This invention generally relates to a level shifter, and more particularly to a level shifter with an active substrate bias to shorten the shifting time.
2. Description of the Related Art
As the semiconductor device and the display technology advances, the consumers can enjoy the new application of the new technology. As to display devices, a cathode ray tube (CRT) had dominated the display market because of its good display quality and low cost. However, CRT cannot provide a good solution for compact size and low power consumption due to its physical limitation. Hence, thin film transistor liquid crystal display (TFT LCD) becomes the main stream because of its advantages of high resolution, compact size, low power consumption and radiation free.
In a TFT LCD, the level shifter is one of the major circuits for the driving circuits; e.g. the scan driver and data driver, of a display panel. The level shifter converts an input signal with a low voltage level to an output signal with a high voltage level. Currently, TFT LCD usually uses low-temperature polysilicon (LTPS) TFT, which has a higher threshold voltage and a lower mobility than the CMOS. Hence, as the number of the pixels increases, the operational speed will correspondingly decrease when the LTPS TFT is used.
FIG. 5 is a circuit of the conventional level shifter, which is generally disposed with the scan driver and the data driver of a display panel, featured to convert an input signal with a low voltage level to an output signal with a high voltage level. Referring to FIG. 5, the level shifter 50 includes a first input transistor Mn1, a first substrate bias circuit 510, a first switch transistor Mp1, a second input transistor Mn2, a second substrate bias circuit 530, and a second switch transistor Mp2. The gate 502 of the first input transistor Mn1 is coupled to the signal source of the first clock signal; the source 506 is grounded. The output terminal 516 of the first substrate bias circuit 510 is coupled to the substrate 508 of the first input transistor Mn1; the input terminal 518 of the first substrate bias circuit 510 is coupled to the gate 502 of the first input transistor Mn1. The drain 524 of the second input transistor Mn2 is coupled to the output terminal 560 wherefrom an output signal Vout is read; the gate 522 is coupled to the signal source of the second clock signal; the source 526 is grounded. The output terminal 536 of the second substrate bias circuit 530 is coupled to the substrate 528 of the second input transistor Mn2; the output terminal 536 is coupled to the gate 522 of the second input transistor Mn2. The drain 544 of the first switch transistor Mp1 is coupled to the voltage source; the gate 542 and the source 546 is coupled to the drain 504 of the first input transistor Mn1. The drain 554 of the second switch transistor Mp2 is coupled to the voltage source; the gate 552 is coupled to the gate 542 of the first switch transistor Mp1; and the source 556 is coupled to the drain 524 of the second input transistor Mn2.
The first substrate bias circuit 510 and the second substrate bias circuit 530 include inverting buffers 512 and 514, and inverting buffers 532 and 534, respectively.
The conventional level shifter operates as follows. When the first clock signal is at logic high and the second clock signal is at logic low, the first input transistor Mn1, the first switch transistor Mp1, and the second switch transistor Mp2 will be turned on, and the second input transistor Mn2 will be turned off. When the first clock signal is changed to be at logic low and the second clock signal is changed to be at logic high, the first input transistor Mn1, the first switch transistor Mp1, and the second switch transistor Mp2 will be turned off. At the same time, the second substrate bias circuit 530 applies a high voltage on the substrate 528 of the second input transistor Mn2 to suppress the threshold voltage of the second input transistor Mn2 and to increase the operational speed of the level shifter 50. However, because the conventional level shifter 50 includes the first and second substrate bias circuits 510 and 530 that takes up additional space, the size of the conventional level shifter 50 is larger than desired. Usually in an LTPS TFT-LCD panel, pixels along with peripheral driving circuits are integrated on a glass substrate, featuring System On Glass (SOG). Therefore, it is desirable to design smaller area of the driving circuit such that display area is increased and fabrication cost is lowered.